DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 198

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.5.6
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space.
(1)
With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The
amount of data that can be accessed at one time is one byte: a word access is performed as two
byte accesses, and a longword access, as four byte accesses.
Figures 6.10 and 6.11 illustrate data alignment control for the 8-bit access space. Figure 6.10
shows the data alignment when the data endian format is specified as big endian. Figure 6.11
shows the data alignment when the data endian format is specified as little endian.
Rev. 2.00 Jun. 28, 2007 Page 172 of 864
REJ09B0341-0200
Figure 6.10 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian)
Longword
8-Bit Access Space
Data
Size
Byte
Word
Endian and Data Alignment
Access
Address
n
n
n
Access
Count
1
2
4
Bus
Cycle
1st
1st
2nd
1st
2nd
3rd
4th
Data Size
Byte
Byte
Byte
Byte
Byte
Byte
Byte
D15
LHWR/LUB
Strobe signal
Data bus
D8 D7
RD
15
31
23
15
7
7
7
LLWR/LLB
D0
24
16
0
8
0
8
0