DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 250

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.12
6.12.1
The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and
register space for the on-chip peripheral modules. The number of cycles necessary for access
differs according the space.
Table 6.25 shows the number of access cycles for each on-chip memory space.
Table 6.25 Number of Access Cycles for On-Chip Memory Spaces
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access in the same way as for external bus clock division.
Table 6.26 lists the number of access cycles for registers of on-chip peripheral modules.
Table 6.26 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Rev. 2.00 Jun. 28, 2007 Page 224 of 864
REJ09B0341-0200
Access Space
On-chip ROM space
On-chip RAM space
Module to be Accessed
DMAC registers
MCU operating mode, clock pulse
generator, power-down control registers,
interrupt controller, bus controller, and DTC
registers
I/O port PFCR registers and WDT registers 2Pφ
I/O port registers other than PFCR, TPU,
PPG, TMR, SCI, A/D, and D/A registers
Internal Bus
Access to Internal Address Space
Access
Read
Write
Read
Write
Read
2Iφ
Number of Cycles
2Pφ
2Iφ
Write
3Iφ
3Pφ
Number of Access Cycles
One Iφ cycle
Six Iφ cycles
One Iφ cycle
One Iφ cycle
Write Data Buffer Function
Disabled
Disabled
Disabled
Enabled