DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 570

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Watchdog Timer (WDT)
13.4
13.4.1
To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1.
During watchdog timer operation, if TCNT overflows without being rewritten because of a system
crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow
while the system is operating normally. Software must prevent TCNT overflows by rewriting the
TCNT value (normally H'00 is written) before overflow occurs. This WDTOVF signal can be used
to reset the LSI internally in watchdog timer mode.
If TCNT overflows when the RSTE bit in RSTCSR is set to 1, a signal that resets this LSI
internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input
to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 133 cycles of Pφ when RSTE = 1 in RSTCSR, and for 130
cycles of Pφ when RSTE = 0 in RSTCSR. The internal reset signal is output for 519 cycles of Pφ.
When RSTE = 1, an internal reset signal is generated. Since the system clock control register
(SCKCR) is initialized, the multiplication ratio of Pφ becomes the initial value.
When RSTE = 0, an internal reset signal is not generated. Neither SCKCR nor the multiplication
ratio of Pφ is changed.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the
entire LSI.
Rev. 2.00 Jun. 28, 2007 Page 544 of 864
REJ09B0341-0200
Operation
Watchdog Timer Mode