DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 17

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Register Descriptions ......................................................................................................... 309
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Activation Sources ............................................................................................................. 318
Location of Transfer Information and DTC Vector Table ................................................. 318
Operation ........................................................................................................................... 322
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10 DTC Bus Release Timing ..................................................................................... 336
8.5.11 DTC Priority Level Control to the CPU ............................................................... 336
DTC Activation by Interrupt.............................................................................................. 337
Examples of Use of the DTC ............................................................................................. 338
8.7.1
8.7.2
8.7.3
Interrupt Sources................................................................................................................ 341
Usage Notes ....................................................................................................................... 342
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
DTC Mode Register A (MRA) ............................................................................. 310
DTC Mode Register B (MRB).............................................................................. 311
DTC Source Address Register (SAR)................................................................... 313
DTC Destination Address Register (DAR)........................................................... 313
DTC Transfer Count Register A (CRA) ............................................................... 313
DTC Transfer Count Register B (CRB)................................................................ 314
DTC Enable Registers A to H (DTCERA to DTCERE)....................................... 315
DTC Control Register (DTCCR) .......................................................................... 316
DTC Vector Base Register (DTCVBR)................................................................ 317
Bus Cycle Division ............................................................................................... 324
Transfer Information Read Skip Function ............................................................ 326
Transfer Information Writeback Skip Function .................................................... 327
Normal Transfer Mode ......................................................................................... 327
Repeat Transfer Mode........................................................................................... 328
Block Transfer Mode ............................................................................................ 330
Chain Transfer ...................................................................................................... 331
Operation Timing.................................................................................................. 333
Number of DTC Execution Cycles ....................................................................... 335
Normal Transfer Mode ......................................................................................... 338
Chain Transfer ...................................................................................................... 339
Chain Transfer when Counter = 0......................................................................... 340
Module Stop Function Setting .............................................................................. 342
On-Chip RAM ...................................................................................................... 342
DMAC Transfer End Interrupt.............................................................................. 342
DTCE Bit Setting.................................................................................................. 342
Chain Transfer ...................................................................................................... 342
Transfer Information Start Address, Source Address,
and Destination Address ....................................................................................... 343
Transfer Information Modification ....................................................................... 343
Endian Format....................................................................................................... 343
Rev. 2.00 Jun. 28, 2007 Page xv of xxiv