DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 528

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 Programmable Pulse Generator (PPG)
11.4
Figure 11.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values. Sequential
output of data of up to 16 bits is possible by writing new output data to NDR before the next
compare match.
11.4.1
If pulse output is enabled, the NDR contents are transferred to PODR and output when the
specified compare match event occurs. Figure 11.3 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
Rev. 2.00 Jun. 28, 2007 Page 502 of 864
REJ09B0341-0200
Operation
Output Timing
Pulse output pin
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)
Pφ
TCNT
NDRH
TGRA
PODRH
PO8 to PO15
Compare match
A signal
Figure 11.2 Schematic Diagram of PPG
Normal output/inverted output
m
N
m
Q
NDER
PODR
Q
C
Output trigger signal
N
n
D
N + 1
Q
NDR
n
D
n
Internal data bus