DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 800

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Power-Down Modes
20.9
Sleep Instruction Exception Handling
Sleep instruction exception handling is the exception handling initiated by the execution of a
SLEEP instruction. Sleep instruction exception handling is always accepted while the program is
in execution.
When the SLPIE bit is set to 0, the execution of a SLEEP instruction does not initiate sleep
instruction exception handling. Instead, the CPU enters the power-down state. After this,
generation of an exception handling request that cancels the power-down state causes the power-
down state to be canceled, after which the CPU starts to handle the exception. When the SLPIE bit
is set to 1, sleep instruction exception handling starts after the execution of a SLEEP instruction.
Transitions to the power-down state are inhibited when sleep instruction exception handling is
initiated, and the CPU immediately starts sleep instruction exception handling.
When a SLEEP instruction is executed while the SLPIE bit is cleared to 0, a transition is made to
the power-down state. The power-down state is canceled by a canceling factor interrupt (see figure
20.5).
When a canceling factor interrupt is generated immediately before the execution of a SLEEP
instruction, exception handling for the interrupt starts. When execution returns from the exception
service routine, the SLEEP instruction is executed to enter the power-down state. In this case, the
power-down state is not canceled until the next canceling factor interrupt is generated (see figure
20.6).
When the SLPIE bit is set to 1 in the service routine for a canceling factor interrupt so that the
execution of a SLEEP instruction will produce sleep instruction exception handling, the operation
of the system is as shown in figure 20.7. Even if a canceling factor interrupt is generated
immediately before the SLEEP instruction is executed, sleep instruction exception handling is
initiated by execution of the SLEEP instruction. Therefore, the CPU executes the instruction that
follows the SLEEP instruction after sleep instruction exception and exception service routine
without shifting to the power-down state.
When the SLPIE bit is set to 1 to start sleep exception handling, clear the SSBY bit in SBYCR
to 0.
Rev. 2.00 Jun. 28, 2007 Page 774 of 864
REJ09B0341-0200