DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 647

IC H8SX/1657 MCU FLASH 120TQFP

DF61657CN35FTV

Manufacturer Part Number
DF61657CN35FTV
Description
IC H8SX/1657 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61657CN35FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
35MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
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Part Number:
DF61657CN35FTV
Manufacturer:
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Quantity:
10 000
14.9.5
The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written
to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR
yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the
TDRE flag is set to 1.
14.9.6
1. When the external clock source is used as a synchronization clock, update TDR by the DMAC
2. When using the DMAC or DTC to read RDR, be sure to set the receive end interrupt (RXI) as
or DTC and wait for at least five Pφ clock cycles before allowing the transmit clock to be
input. If the transmit clock is input within four clock cycles after TDR modification, the SCI
may malfunction (figure 14.33).
the DMAC or DTC activation source.
Figure 14.33 Sample Transmission using DTC in Clocked Synchronous Mode
Relation between Writing to TDR and TDRE Flag
Restrictions on Using DMAC or DTC
SCK
TDRE
Serial data
Note: When external clock is supplied, t must be more than four clock cycles.
t
LSB
D0
D1
D2
D3
Section 14 Serial Communication Interface (SCI)
D4
Rev. 2.00 Jun. 28, 2007 Page 621 of 864
D5
D6
D7
REJ09B0341-0200

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