DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet
DF61657CN35FTV
Specifications of DF61657CN35FTV
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DF61657CN35FTV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8SX/1657 Group 32 Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change ...
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Rev. 2.00 Jun. 28, 2007 Page ii of xxiv ...
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users ...
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Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...
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Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...
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Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator DTC Data transfer controller INTC Interrupt controller PPG Programmable pulse generator SCI ...
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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Functions.............................................................................................. 2 1.2 List of Products ...................................................................................................................... 8 1.3 Block Diagram ....................................................................................................................... 9 1.4 Pin Descriptions ................................................................................................................... 10 1.4.1 Pin Assignments ..................................................................................................... 10 1.4.2 Pin Functions .......................................................................................................... 11 ...
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Register DirectRn ............................................................................................... 52 2.8.2 Register Indirect@ERn....................................................................................... 52 2.8.3 Register Indirect with Displacement @(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)....................................................... 52 2.8.4 Index Register Indirect with Displacement@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 52 2.8.5 Register Indirect with Post-Increment, ...
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Interrupts after Reset............................................................................................... 78 4.3.3 On-Chip Peripheral Functions after Reset Release ................................................. 79 4.4 Traces................................................................................................................................... 81 4.5 Address Error ....................................................................................................................... 82 4.5.1 Address Error Source.............................................................................................. 82 4.5.2 Address Error Exception Handling ......................................................................... 83 4.6 Interrupts.............................................................................................................................. 84 4.6.1 Interrupt Sources..................................................................................................... ...
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Usage Notes ....................................................................................................................... 125 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 125 5.8.2 Instructions that Disable Interrupts....................................................................... 126 5.8.3 Times when Interrupts are Disabled ..................................................................... 126 5.8.4 Interrupts during Execution of EEPMOV Instruction .......................................... 126 5.8.5 Interrupts during ...
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Byte Control SRAM Interface ........................................................................................... 188 6.7.1 Byte Control SRAM Space Setting....................................................................... 188 6.7.2 Data Bus................................................................................................................ 188 6.7.3 I/O Pins Used for Byte Control SRAM Interface ................................................. 189 6.7.4 Basic Timing......................................................................................................... 190 6.7.5 Wait Control ......................................................................................................... 192 6.7.6 Read ...
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Bus Arbitration .................................................................................................................. 227 6.14.1 Operation .............................................................................................................. 227 6.14.2 Bus Transfer Timing............................................................................................. 228 6.15 Bus Controller Operation in Reset ..................................................................................... 229 6.16 Usage Notes ....................................................................................................................... 230 Section 7 DMA Controller (DMAC)................................................................. 233 7.1 Features.............................................................................................................................. 233 7.2 Input/Output Pins............................................................................................................... 236 ...
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Register Descriptions ......................................................................................................... 309 8.2.1 DTC Mode Register A (MRA) ............................................................................. 310 8.2.2 DTC Mode Register B (MRB).............................................................................. 311 8.2.3 DTC Source Address Register (SAR)................................................................... 313 8.2.4 DTC Destination Address Register (DAR)........................................................... 313 8.2.5 DTC Transfer Count Register A ...
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Section 9 I/O Ports............................................................................................. 345 9.1 Register Descriptions......................................................................................................... 352 9.1.1 Data Direction Register (PnDDR and I)............. 353 9.1.2 Data Register (PnDR ...
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Timer Control Register (TCR).............................................................................. 412 10.3.2 Timer Mode Register (TMDR) ............................................................................. 417 10.3.3 Timer I/O Control Register (TIOR) ...................................................................... 418 10.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 436 10.3.5 Timer Status Register (TSR)................................................................................. 438 10.3.6 Timer Counter (TCNT)......................................................................................... 442 ...
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Section 11 Programmable Pulse Generator (PPG)............................................ 491 11.1 Features.............................................................................................................................. 491 11.2 Input/Output Pins............................................................................................................... 492 11.3 Register Descriptions......................................................................................................... 493 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 493 11.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 495 11.3.3 Next ...
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Timing of Timer Output at Compare Match ......................................................... 528 12.5.4 Timing of Counter Clear by Compare Match ....................................................... 529 12.5.5 Timing of TCNT External Reset........................................................................... 529 12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 530 12.6 Operation with Cascaded ...
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Section 14 Serial Communication Interface (SCI)............................................ 551 14.1 Features.............................................................................................................................. 551 14.2 Input/Output Pins............................................................................................................... 553 14.3 Register Descriptions......................................................................................................... 554 14.3.1 Receive Shift Register (RSR) ............................................................................... 555 14.3.2 Receive Data Register (RDR)............................................................................... 556 14.3.3 Transmit Data Register (TDR).............................................................................. 556 14.3.4 Transmit Shift ...
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Clock Output Control............................................................................................ 616 14.8 Interrupt Sources................................................................................................................ 618 14.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 618 14.8.2 Interrupts in Smart Card Interface Mode .............................................................. 619 14.9 Usage Notes ....................................................................................................................... 620 14.9.1 Module Stop State Setting .................................................................................... 620 ...
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Register Descriptions......................................................................................................... 644 16.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 644 16.3.2 D/A Control Register 01 (DACR01) .................................................................... 645 16.4 Operation ........................................................................................................................... 647 16.5 Usage Notes ....................................................................................................................... 648 16.5.1 Module Stop State Setting .................................................................................... 648 16.5.2 ...
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System Clock Control Register (SCKCR) ............................................................ 746 19.2 Oscillator............................................................................................................................ 749 19.2.1 Connecting Crystal Resonator .............................................................................. 749 19.2.2 External Clock Input............................................................................................. 750 19.3 PLL Circuit ........................................................................................................................ 750 19.4 Frequency Divider ............................................................................................................. 751 19.5 Usage Notes ....................................................................................................................... 751 19.5.1 Notes on ...
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Writing to MSTPCRA, MSTPCRB, and MSTPCRC........................................... 778 Section 21 List of Registers............................................................................... 779 21.1 Register Addresses (Address Order).................................................................................. 780 21.2 Register Bits....................................................................................................................... 790 21.3 Register States in Each Operating Mode ........................................................................... 803 Section 22 Electrical Characteristics ................................................................. 813 22.1 ...
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Features The core of each product in the H8SX/1657 Group of CISC (complex instruction set computer) microcomputers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of other Renesas Technology-original ...
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Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of H8SX/1657 Group products in outline. Table 1.1 Overview of Functions Module/ Classification Function Memory ROM RAM CPU CPU Operating mode Rev. 2.00 Jun. 28, 2007 Page 2 ...
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Module/ Classification Function CPU MCU operating mode Interrupt Interrupt (source) controller (INTC) Description Mode 1: User boot mode (selected by driving the MD2 and MD1 pins low and driving the MD0 pin high) Mode 2: Boot mode (selected by driving ...
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Section 1 Overview Module/ Classification Function DMA DMA controller (DMAC) DTC Data transfer controller (DTC) External bus Bus extension controller (BSC) Rev. 2.00 Jun. 28, 2007 Page 4 of 864 REJ09B0341-0200 Description • Four-channel DMA transfer available • Three activation ...
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Module/ Classification Function Clock Clock pulse generator (CPG) A/D converter A/D converter (ADC) D/A converter D/A converter (DAC) Description • One clock generation circuit available • Separate clock signals are provided for each of functional modules (detailed below) and each ...
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Section 1 Overview Module/ Classification Function Timer 8-bit timer (TMR) 16-bit timer pulse unit (TPU) Program- mable pulse generator (PPG) Watchdog timer Watchdog timer (WDT) Serial interface Serial communi- cation interface (SCI) Smart card/ SIM Rev. 2.00 Jun. 28, 2007 ...
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Module/ Classification Function I/O ports Package Operating frequency/ Power supply voltage Operating peripheral temperature (°C) Description • Nine CMOS input-only pins • 81 CMOS input/output pins • Eight large-current drive pins (port 3) • 40 pull-up resistors • 16 open ...
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Section 1 Overview 1.2 List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.2 List of Products Product Type No. ROM Capacity R5F61657CFTV 768 Kbytes R5F61656CFTV 512 ...
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Block Diagram RAM ROM H8SX CPU DTC Clock pulse generator [Legend] CPU: Central processing unit DTC: Data transfer controller BSC: Bus controller DMAC: DMA controller WDT: Watchdog timer Interrupt controller (TMR_0, TMR_1) (TMR_2, TMR_3) BSC TPU × 6 channels ...
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Section 1 Overview 1.4 Pin Descriptions 1.4.1 Pin Assignments P62/TMO2/SCK4/DACK2/IRQ10-B 91 PLLVcc 92 P63/TMRI3/DREQ3/IRQ11-B 93 PLLVss 94 P64/TMCI3/TEND3 95 P65/TMO3/DACK3 96 MD0 97 P50/AN0/IRQ0-B 98 P51/AN1/IRQ1-B 99 P52/AN2/IRQ2-B 100 AVcc 101 P53/AN3/IRQ3-B 102 AVss 103 P54/AN4/IRQ4-B 104 Vref 105 P55/AN5/IRQ5-B ...
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Pin Functions Table 1.3 Pin Functions Classification Pin Name Power supply PLLV CC PLLV SS Clock XTAL EXTAL Bφ Operating mode MD2 to MD0 control RES System control STBY EMLE Address bus A23 ...
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Section 1 Overview Classification Pin Name BACK Bus control BS-A/BS RD/WR LHWR LLWR LUB LLB CS0 CS1 CS2-A/CS2-B CS3 CS4 CS5-A/CS5-B CS6-A/CS6-B CS7-A/CS7-B WAIT Rev. 2.00 Jun. 28, 2007 Page 12 of 864 REJ09B0341-0200 I/O Description Output ...
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Classification Pin Name Interrupt NMI IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B DREQ0-A/DREQ0-B DMA controller DREQ1-A/DREQ1-B (DMAC) DREQ2 DREQ3 DACK0-A/DACK0-B DACK1-A/DACK1-B DACK2 DACK3 TEND0-A/TEND0-B TEND1-A/TEND1-B TEND2 TEND3 16-bit timer TCLKA-A/TCLKA-B pulse unit (TPU) TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B ...
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Section 1 Overview Classification Pin Name 16-bit timer TIOCA2 pulse unit (TPU) TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Programmable PO15 to PO0 pulse generator (PPG) 8-bit timer TMO0 to TMO3 (TMR) TMCI0 to TMCI3 TMRI0 to TMRI3 ...
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Classification Pin Name A/D converter AN7 to AN0 ADTRG0 D/A converter DA1, DA0 A/D converter D/A converter AV SS Vref I/O ports P17 to P10 P27 to P20 P37 to P30 P57 to P50 P65 to P60 PA7 ...
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Section 1 Overview Rev. 2.00 Jun. 28, 2007 Page 16 of 864 REJ09B0341-0200 ...
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The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward- compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
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Section 2 CPU • Two base registers Vector base register Short address base register • 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes • High-speed operation All frequently-used instructions executed in one or two ...
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CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. CPU operating modes 2.2.1 Normal Mode The exception vector table and stack ...
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Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the ...
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Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program ...
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Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...
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Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP Reserved (a) ...
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Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...
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Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...
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Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...
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General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. SP (ER7) 2.5.2 Program Counter (PC) ...
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Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can ...
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Section 2 CPU Initial Bit Bit Name Value 2 Z Undefined R Undefined R Undefined R/W 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask ...
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Initial Bit Bit Name Value 2.5.5 Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are ...
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Section 2 CPU 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword ...
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Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in ...
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Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 5 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC [Legend] B: Byte size W: Word size L: Longword size Notes: 1. ...
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Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data MOV B/W/L ...
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Classifi- cation Instruction Size Arithmetic ADDS, SUBS L operations DAA, DAS B MULXU, B/W DIVXU MULU, DIVU W/L MULXS, B/W DIVXS MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B MAC CLRMAC LDMAC STMAC ...
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Section 2 CPU Classifi- cation Instruction Size Bit BSET, BCLR, B manipu- BNOT, BTST, lation BSET/cc, BCLR/cc BAND, BIAND, B BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ BFLD B BFST B Branch BRA/BS BRA/BC* BSR/BS, ...
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Size of data to be added with a displacement 5. Only @ERn− is available 6. When the number of bits to be shifted When the number of bits to be shifted ...
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Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd ...
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Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE → (EAs) MOVTPE* B @SP+ → Rn POP W/L ...
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Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of ...
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Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted ...
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Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVU W/L Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient bits ÷ 32 bits → 32-bit quotient. ...
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Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) AND B/W/L Performs a logical AND operation on data between immediate data, general registers, and memory. (EAd) ∨ #IMM → (EAd), (EAd) ...
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Section 2 CPU Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified ...
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Instruction Size Function C ∨ (<bit-No.> of <EAd>) → C BOR B ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The ...
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Section 2 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit ...
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Table 2.11 System Control Instructions Instruction Size Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. RTE/L Returns from an exception-handling routine, restoring data from the stack to multiple general registers. SLEEP Causes ...
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Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...
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Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode ...
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Section 2 CPU 2.8.1 Register DirectRn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be ...
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Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement@ERn+, @−ERn, @+ERn, or @ERn− (1) Register indirect with post-increment@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ...
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Section 2 CPU Example 1: MOV.W R0, @ER0+ When ER0 before execution is H'12345678, H'567A is written at H'12345678. Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. ...
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Table 2.13 Absolute Address Access Ranges Absolute Normal Address Mode Data area 8 bits A consecutive 256-byte area (the upper address is set in SBR) (@aa:8) 16 bits H'0000 to (@aa:16) H'FFFF 32 bits (@aa:32) Program area 24 bits (@aa:24) ...
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Section 2 CPU 2.8.7 Immediate#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the ...
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Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed 8-bit absolute address in the instruction code. ...
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Section 2 CPU 2.8.11 Extended Memory Indirect@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: ...
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Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement op r disp ...
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Section 2 CPU Table 2.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with ...
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Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state the CPU and ...
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Section 2 CPU Exception-handling state Request for exception handling Program execution state A transition to the reset state occurs whenever the RES signal goes low. Note transition can also be made to the reset state when the watchdog ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has seven operating modes (modes 1 to 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Table 3.1 lists MCU operating mode settings. ...
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Section 3 MCU Operating Modes Modes are external extended modes, in which the external memory and devices can be accessed. In the external extended modes, the external address space can be designated as 8-bit or 16-bit address ...
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Bit Bit Name Initial Value R/W MDS3 Undefined* 10 MDS2 Undefined* 9 MDS1 Undefined* 8 MDS0 Undefined* ...
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Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit 15 14 ...
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Bit Bit Name Initial Value R/W EXPE Undefined* 8 RAME 1 All 0 1 DTCMD 1 Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch. ...
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 This is the user boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the ...
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Mode 6 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access ...
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Section 3 MCU Operating Modes 3.3.7 Pin Functions Table 3.3 lists the pin functions in each operating mode. Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode) MCU Port A Operation PA7 PA6 to PA2 to Mode PA 3 ...
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Address Map 3.4.1 Address Map Figure 3.1 show the address map in each operating mode. Mode 1 User boot mode (Advanced mode) H'000000 On-chip ROM H'0C0000 External address space reserved area* * H'FD9000 3 Reserved area* H'FDC000 ...
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Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 2 Reserved area* H'FDC000 External address space H'FF6000 On-chip RAM/ external address 1 space* H'FFC000 External address space H'FFEA00 On-chip I/O ...
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Mode 1 User boot mode (Advanced mode) H'000000 On-chip ROM H'080000 (Access-prohibited space) H'0C0000 External address space reserved area* * H'FD9000 3 Reserved area* H'FDC000 External address space reserved area* * H'FF6000 2 On-chip RAM* H'FFC000 ...
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Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 2 Reserved area* H'FDC000 External address space H'FF6000 On-chip RAM/ external address 1 space* H'FFC000 External address space H'FFEA00 On-chip I/O ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector ...
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Exception Source User area (not used) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 Reserved for system use 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. Not available in this ...
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Section 4 Exception Handling 4.3 Reset A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES ...
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On-Chip Peripheral Functions after Reset Release After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF, respectively, and all modules except the DTC and DMAC enter the module stop state. Consequently, on-chip peripheral module ...
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Section 4 Exception Handling Bφ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For ...
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Section 4 Exception Handling 4.5 Address Error 4.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description ...
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Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents ...
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Section 4 Exception Handling 4.6 Interrupts 4.6.1 Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Interrupt Sources Type Source NMI NMI pin (external input) Pins IRQ0 to IRQ11 ...
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Instruction Exception Handling There are three instructions that cause exception handling: trap instruction, sleep instruction, and illegal instruction. 4.7.1 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed ...
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Section 4 Exception Handling 4.7.2 Sleep Instruction Exception Handling The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The ...
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Exception Handling by Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by the slot illegal instruction ...
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Section 4 Exception Handling 4.8 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of exception handling. Advanced mode SP Interrupt control mode 0 Note: * Ignored on return. Figure 4.3 Stack Status after Exception Handling Rev. ...
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Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer ...
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Section 4 Exception Handling Rev. 2.00 Jun. 28, 2007 Page 90 of 864 REJ09B0341-0200 ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISCR IER Internal interrupt sources Source selector WOVI to TEI4 DTCER [Legend] ...
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Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ11 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7 6 Bit Name Initial Value Initial Bit Bit Name Value ...
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CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC and DMAC transfer. The ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 3 IPSETE 0 2 CPUP2 0 1 CPUP1 0 0 CPUP0 0 Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits ...
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Interrupt Priority Registers and L (IPRA to IPRC, IPRE to IPRI, IPRK, and IPRL) IPR sets priory (levels for interrupts other than NMI. Setting a value in the range ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 10 IPR10 1 9 IPR9 1 8 IPR8 1 IPR6 1 5 IPR5 1 4 IPR4 1 Rev. 2.00 Jun. 28, 2007 Page 98 ...
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Initial Bit Bit Name Value 2 IPR2 1 1 IPR1 1 0 IPR0 1 5.3.4 IRQ Enable Register (IER) IER enables or disables interrupt requests IRQ11 to IRQ0. Bit 15 14 Bit Name Initial Value 0 0 R/W ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 10 IRQ10E 0 9 IRQ9E 0 8 IRQ8E 0 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ11 to IRQ0. Upon changing the setting of ISCR, IRQnF ( 11) in ISR ...
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Section 5 Interrupt Controller • ISCRH Initial Bit Bit Name Value All 0 7 IRQ11SR 0 6 IRQ11SF 0 5 IRQ10SR 0 4 IRQ10SF 0 3 IRQ9SR 0 2 IRQ9SF 0 1 IRQ8SR 0 0 IRQ8SF ...
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ISCRL Initial Bit Bit Name Value 15 IRQ7SR 0 14 IRQ7SF 0 13 IRQ6SR 0 12 IRQ6SF 0 11 IRQ5SR 0 10 IRQ5SF 0 9 IRQ4SR 0 8 IRQ4SF 0 R/W Description R/W IRQ7 Sense Control Rise IRQ7 Sense ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 7 IRQ3SR 0 6 IRQ3SF 0 5 IRQ2SR 0 4 IRQ2SF 0 3 IRQ1SR 0 2 IRQ1SF 0 1 IRQ0SR 0 0 IRQ0SF 0 Rev. 2.00 Jun. 28, 2007 Page 104 ...
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IRQ Status Register (ISR) ISR is an IRQ11 to IRQ0 interrupt request register. Bit 15 14 Bit Name Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ7F IRQ6F Initial Value 0 0 R/W ...
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Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ11 to IRQ0. The IRQ interrupt used to leave software standby mode should not be set as ...
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Interrupt Sources 5.4.1 External Interrupts There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always ...
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Section 5 Interrupt Controller A block diagram of interrupts IRQn is shown in figure 5.2. Corresponding bit in ICR Input buffer IRQn input [Legend Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing ...
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Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, ...
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Section 5 Interrupt Controller Classifi- cation Interrupt Source Reserved for system use A/D ADI Reserved for system use TPU_0 TGI0A TGI0B TGI0C TGI0D TCI0V TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C ...
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Classifi- cation Interrupt Source TPU_5 TGI5A TGI5B TCI5V TCI5U Reserved for system use TMR_0 CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_2 CMIA2 CMIB2 OVl2 TMR_3 CMIA3 CMIB3 OVI3 DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 Reserved for system use ...
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Section 5 Interrupt Controller Classifi- cation Interrupt Source Reserved for system use SCI_0 ERI0 RXI0 TXI0 TEI0 SCI_1 ERI1 RXI1 TXI1 TEI1 SCI_2 ERI2 RXI2 TXI2 TEI2 Reserved for system use SCI_4 ERI4 RXI4 TXI4 TEI4 Reserved ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by ...
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Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure ...
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Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level ( bits) in EXR of the CPU and the IPR setting. There are eight levels ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance Rev. 2.00 Jun. 28, 2007 Page 116 of 864 REJ09B0341-0200 Program execution state No Interrupt generated? Yes ...
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Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip ...
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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used ...
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Table 5.5 Number of Execution States in Interrupt Handling Routine On-Chip Symbol Memory Vector fetch Instruction fetch Stack manipulation [Legend] m: Number of wait cycles in an external device access. 5.6.5 ...
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Section 5 Interrupt Controller Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller. Interrupt request On-chip DMAC select peripheral circuit Interrupt request module clear signal Interrupt request IRQ interrupt Interrupt request clear signal Interrupt controller Figure ...
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When the same interrupt source is set as both the DTC and DMAC activation source and CPU interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1, ...
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Section 5 Interrupt Controller (4) Usage Note The interrupt sources of the SCI and A/D converter are cleared according to the setting shown in table 5.6, when the DTC or DMAC reads/writes the prescribed register. To initiate multiple channels for ...
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There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU ...
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Section 5 Interrupt Controller Table 5.8 Example of Priority Control Function Setting and Control State Interrupt Control CPUPCE in Mode CPUPCR Rev. 2.00 Jun. 28, 2007 Page 124 of 864 REJ09B0341-0200 CPUP2 to DTCP2 ...
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Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to ...
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Section 5 Interrupt Controller Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to activate the DTC, DTC activation and the interrupt exception handling by the CPU are both executed. When changing the DTC enable ...
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Interrupts during Execution of MOVMD and MOVSD Instructions With the MOVMD or MOVSD instruction interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved ...
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Section 5 Interrupt Controller Rev. 2.00 Jun. 28, 2007 Page 128 of 864 REJ09B0341-0200 ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus ...
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Section 6 Bus Controller (BSC) • Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas Idle cycles can be inserted before the external write access after an external read access Idle cycles can be ...
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A block diagram of the bus controller is shown in figure 6.1. CPU address bus DMAC address bus DTC address bus Internal bus control signals CPU bus mastership acknowledge signal DTC bus mastership acknowledge signal DMAC bus mastership acknowledge signal ...
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Section 6 Bus Controller (BSC) 6.2 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • ...
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Bus Width Control Register (ABWCR) ABWCR specifies the data bus width for each area in the external address space. Bit 15 14 Bit Name ABWH7 ABWH6 Initial Value 1 1 R/W R/W R/W Bit 7 6 Bit Name ABWL7 ...
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Section 6 Bus Controller (BSC) 6.2.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit 15 14 Bit Name AST7 ...
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Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. • WTCRA Bit 15 14 Bit Name W72 Initial Value 0 1 ...
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Section 6 Bus Controller (BSC) • WTCRA Initial Bit Bit Name Value W72 1 13 W71 1 12 W70 1 W62 1 9 W61 1 8 W60 1 Rev. ...
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Initial Bit Bit Name Value 6 W52 1 5 W51 1 4 W50 1 W42 1 1 W41 1 0 W40 1 R/W Description R/W Area 5 Wait Control R/W These bits select ...
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Section 6 Bus Controller (BSC) • WTCRB Initial Bit Bit Name Value W32 1 13 W31 1 12 W30 1 W22 1 9 W21 1 8 W20 1 Rev. ...
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Initial Bit Bit Name Value 6 W12 1 5 W11 1 4 W10 1 W02 1 1 W01 1 0 W00 1 R/W Description R/W Area 1 Wait Control R/W These bits select ...
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Section 6 Bus Controller (BSC) 6.2.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O ...
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Bφ RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) CS Assertion Period Control Registers (CSACR) 6.2.5 CSACR selects whether or not the assertion periods of the chip ...
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Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 15 CSXH7 0 14 CSXH6 0 13 CSXH5 0 12 CSXH4 0 11 CSXH3 0 10 CSXH2 0 9 CSXH1 0 8 CSXH0 0 7 CSXT7 0 6 CSXT6 0 ...
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Bφ Address CSn AS BS RD/WR RD Read Data bus LHWR, LLWR Write Data bus Figure 6.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0) 6.2.6 Idle Control Register (IDLCR) ...
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Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 15 IDLS3 1 14 IDLS2 1 13 IDLS1 1 12 IDLS0 1 11 IDLCB1 1 10 IDLCB0 1 9 IDLCA1 1 8 IDLCA0 1 Rev. 2.00 Jun. 28, 2007 Page ...
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Initial Bit Bit Name Value 7 IDLSEL7 0 6 IDLSEL6 0 5 IDLSEL5 0 4 IDLSEL4 0 3 IDLSEL3 0 2 IDLSEL2 0 1 IDLSEL1 0 0 IDLSEL0 0 6.2.7 Bus Control Register 1 (BCR1) BCR1 is used for selection ...
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Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 14 BREQOE 0 13, 12 All 0 11, 10 All 0 9 WDBE 0 8 WAITE 0 7 DKC 0 All ...
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Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU, DMAC, and DTC, and enabling/disabling of the write data buffer function to the peripheral modules. Bit 7 6 Bit Name Initial Value ...
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Section 6 Bus Controller (BSC) 6.2.9 Endian Control Register (ENDIANCR) ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little ...
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SRAM Mode Control Register (SRAMCR) SRAMCR specifies the bus interface of each area in the external address space as a basic bus interface or a byte control SRAM interface. In areas specified as 8-bit access space by ABWCR, the ...
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Section 6 Bus Controller (BSC) 6.2.11 Burst ROM Interface Control Register (BROMCR) BROMCR specifies the burst ROM interface. Bit 15 14 Bit Name BSRM0 BSTS02 Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name BSRM1 BSTS12 Initial ...
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Initial Bit Bit Name Value 9 BSWD01 0 8 BSWD00 0 7 BSRM1 0 6 BSTS12 0 5 BSTS11 0 4 BSTS10 0 All 0 1 BSWD11 0 0 BSWD10 0 R/W Description R/W Area 0 Burst ...
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Section 6 Bus Controller (BSC) 6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR specifies the address/data multiplexed I/O interface. When the bus interface of each area in the external address space is specified as a basic interface or a byte ...
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Bus Configuration Figure 6.4 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. • Internal system bus A bus that connects the CPU, DTC, DMAC, on-chip RAM, on-chip ...
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Section 6 Bus Controller (BSC) 6.4 Multi-Clock Function and Number of Access Cycles The internal functions of this LSI operate synchronously with the system clock (Iφ), the peripheral module clock (Pφ), or the external bus clock (Bφ). Table 6.1 shows ...
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The frequency of each synchronization clock (Iφ, Pφ, and Bφ) is specified by the system clock control register (SCKCR) independently. For further details, see section 19, Clock Pulse Generator. There will be cases when Pφ and Bφ are equal to ...
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Section 6 Bus Controller (BSC) Iφ Bφ Address CSn AS RD Read D15 LHWR LLWR Write D15 RD/WR Figure 6.5 System Clock: External Bus Clock = 4:1, External 2-State ...
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Divided clock synchronization cycle T sy Iφ Bφ Address CSn AS RD Read D15 LHWR LLWR Write D15 RD/WR Figure 6.6 System Clock: External Bus Clock = 2:1, External ...
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Section 6 Bus Controller (BSC) 6.5 External Bus 6.5.1 Input/Output Pins Table 6.2 shows the pin configuration of the bus controller and table 6.3 shows the pin functions on each interface. Table 6.2 Pin Configuration Name Bus cycle start Address ...
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Name Low-low write/lower-lower byte select Chip select 0 Chip select 1 Chip select 2 Chip select 3 Chip select 4 Chip select 5 Chip select 6 Chip select 7 Wait Bus request Bus request acknowledge Bus request output Data transfer ...
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Section 6 Bus Controller (BSC) Name Data transfer acknowledge 1 (DMAC_1) Data transfer acknowledge 0 (DMAC_0) External bus clock Table 6.3 Pin Functions in Each Interface Initial State Single- Pin Name 16 8 Chip Output Output Bφ CS0 Output ...
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Area Division The bus controller divides the 16-Mbyte address space into eight areas, and performs bus control for the external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. Figure 6.7 ...
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Section 6 Bus Controller (BSC) 6.5.3 Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas The signal outputs low when the corresponding external address space area is accessed. Figure 6.8 shows ...
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Bφ CS5 CS6 Output waveform Address bus Figure 6.9 Timing When CS Signal is Output to the Same Pin 6.5.4 External Bus Interface The type of the external bus interfaces, bus width, endian format, number of access cycles, and strobe ...
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Section 6 Bus Controller (BSC) Table 6.5 Areas Specifiable for Each Interface Interface Basic interface Byte control SRAM interface Burst ROM interface Address/data multiplexed I/O interface (1) Bus Width A bus width bits can be selected ...
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Number of Access Cycles: (a) Basic Bus Interface The number of access cycles in the basic bus interface can be specified as two or three cycles by the ASTCR. An area specified as 2-state access is specified as 2-state ...
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Section 6 Bus Controller (BSC) (d) Address/data multiplexed I/O interface The number of access cycles in data cycle of the address/data multiplexed I/O interface is the same as that in the basic bus interface. The number of access cycles in ...
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Area and External Bus Interface (1) Area 0 Area 0 includes on-chip ROM*. All of area 0 is used as external address space in on-chip ROM disabled extended mode, and the space excluding on-chip ROM is external address space ...
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Section 6 Bus Controller (BSC) Table 6.8 Area 1 External Interface Interface Basic bus interface Byte control SRAM interface Burst ROM interface Setting prohibited (3) Area 2 In externally extended mode, all of area 2 is external address space. When ...
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Table 6.10 Area 3 External Interface Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited (5) Area 4 In externally extended mode, all of area 4 is external address space. When area 4 external address ...
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Section 6 Bus Controller (BSC) (6) Area 5 Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area 5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that the ...
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Table 6.13 Area 6 External Interface Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited (8) Area 7 Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O register ...
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Section 6 Bus Controller (BSC) 6.5.6 Endian and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data ...
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Access Data Address Size n Byte n Word n Longword Figure 6.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (2) 16-Bit Access Space With the 16-bit access space, the upper byte data bus (D15 to D8) and ...
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Section 6 Bus Controller (BSC) Access Access Size Address Even Byte (2n) Odd (2n+1) Even Word (2n) Odd (2n+1) Even Longword (2n) Odd (2n+1) Figure 6.12 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian) Access Access ...