DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 794

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Power-Down Modes
20.7
20.7.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip
peripheral functions other than the SCI, and the states of the I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state or retain the output
state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, allowing power
consumption to be significantly reduced.
If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby
mode. The WDT should be stopped before the SLEEP instruction execution.
20.7.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ11*), or
by means of the RES pin or STBY pin.
1. Clearing by interrupt
2. Clearing by RES pin
3. Clearing by STBY pin
Rev. 2.00 Jun. 28, 2007 Page 768 of 864
REJ09B0341-0200
When an NMI or IRQ0 to IRQ11* interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to
the entire LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ11* interrupt, set the
corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts
IRQ0 to IRQ11* is generated. Software standby mode cannot be cleared if the interrupt has
been masked on the CPU side or has been designated as a DTC activation source.
Note: * By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ11 can be used as a software
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception
handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Software Standby Mode
Transition to Software Standby Mode
Clearing Software Standby Mode
standby mode clearing source.