DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 784

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Power-Down Modes
20.2.1
SBYCR controls software standby mode.
Rev. 2.00 Jun. 28, 2007 Page 758 of 864
REJ09B0341-0200
Bit
15
14
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
SSBY
OPE
Standby Control Register (SBYCR)
SLPIE
SSBY
R/W
R/W
15
0
7
0
Initial
Value
0
1
OPE
R/W
R/W
14

1
6
0
R/W
R/W
R/W
R/W
R/W
13


0
5
0
Description
Software Standby
Specifies the transition mode after executing the SLEEP
instruction
0: Shifts to sleep mode after the SLEEP instruction is
1: Shifts to software standby mode after the SLEEP
This bit remains set to 1 when software standby mode is
cleared by using external interrupts and a transition to the
normal operation is made. For clearing, write 0 to this bit.
When the WDT is used as the watchdog timer, the setting
of this bit is disabled. In this case, a transition is always
made to sleep mode or all-module-clock-stop mode after
the SLEEP instruction is executed.
This bit should be cleared to 0 when setting the SLPIE bit
to 1.
Output Port Enable
Specifies whether the output of the address bus and bus
control signals (CS0 to CS7, AS, RD, HWR, and LWR) is
retained or set to the high-impedance state in software
standby mode.
0: In software standby mode, address bus and bus
1: In software standby mode, address bus and bus
executed
instruction is executed
control signals are high-impedance
control signals retain output state
STS4
R/W
R/W
12

0
4
0
STS3
R/W
R/W
11

1
3
0
STS2
R/W
R/W
10

1
2
0
STS1
R/W
R/W

9
1
1
0
STS0
R/W
R/W

8
1
0
0