IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 93

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Using HIL
HIL Design Example
© June 2010 Altera Corporation
5. Double-click the frequency sweep HIL block to display the Hardware in the loop
6. Select the Quartus II project by browsing into the FreqSweep_dspbuilder
7. Select Clock from the list of available clock pins.
8. Select aclr from the list of available reset pins.
9. Identify the signed ports:
10. Select the reset level to be Active_High.
11. Select the mode of operation by turning off Burst Mode.
12. Click Next page. to display the second page of the Hardware in the loop dialog
13. Specify a value for the FPGA device and click Compile with Quartus II to
14. Click Scan Jtag to find available cables and hardware devices in the chain.
15. Select the JTAG download cable that references the required FPGA device and
16. Click Close.
dialog box.
directory to locate the FreqSweep.qpf file.
1
1
■
■
box.
compile the HIL design.
1
click Configure FPGA to program the FPGA on the board.
Select the Input port and click Unsigned.
Select each output port (OutputCordic and OutputFilter) and click Signed.
The full path to this file is visible in the dialog box when you select this file.
HIL does not support multiple clock domains and only the specified signal
is the HIL clock signal. The HIL treats any other clocks in your design as
input signals.
If no output writes to the MATLAB command window, check that the
original Quartus II project is up-to-date and compiles with he same version
of the Quartus II software that compiles your Simulink model.
Preliminary
DSP Builder Standard Blockset User Guide
5–5