IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 242

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–34
Table 2–51. SOP Tap Block Parameters
Table 2–52. SOP Tap Block I/O Formats
DSP Builder Standard Blockset Libraries
Bus Type
Input Number of Bits
Number of Taps
Use Enable Port
Use Asynchronous Clear Port On or Off
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
...
In
I(n+1)
I(n+2)
O1
1))].[2R]
O2
Simulink (2),
[L].[R]
[L].[R]
[L].[R]
[L].[R]
[2L + cell(log2(N +
Table
is an input port. O1
Name
2–52:
(3)
Table 2–50. SOP Tap Block Inputs and Outputs
Table 2–51
Table 2–52
Figure 2–20
din
c
c
ena
aclr
q
dout
I1: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0)
...
In: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0)
I(n+1): STD_LOGIC
I(n+2): STD_LOGIC
O1: out STD_LOGIC_VECTOR({2L + cell(log2(N + 1)) + 2R - 1} DOWNTO 0)
O2: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0)
0
3
, c
[L].[R]
Signal
1
is an output port.
Signed Integer,
Unsigned Integer
>= 0
(Parameterizable)
2 or 4
On or Off
, c
shows the SOP Tap block parameters.
shows the SOP Tap block I/O formats.
2
shows an example with the SOP Tap block.
,
Value
(Note 1)
Input
Input
Input
Input
Output
Output
Direction
The bus number format that you want to use for the counter.
Specify the number of bits.
The number of taps.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Preliminary
Data input.
2 or 4 tap coefficients.
Optional clock enable.
Optional asynchronous clear.
Result.
Shifted input data.
VHDL
Description
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
Explicit
...
Explicit
Explicit
Explicit
Type
(4)
SOP Tap