IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 307

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Interfaces Library
Avalon-ST Source
Table 5–16. Avalon-ST Source Block Parameters
© June 2010 Altera Corporation
Specify Clock
Clock
Data Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Symbol Width
Use endofpacket
Use startofpacket
Use empty
Ready Latency
Name
On or Off
User defined
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
1–512
On or Off
On or Off
On or Off
0 or 1
Figure 5–13
Figure 5–13. Avalon-ST Source Block with All Signals Enabled
Value
shows an Avalon-ST Source block with all signals enabled.
Turn on to explicitly specify the clock name.
Specifies the clock signal name.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
Read and write buses must have the same number of bits.
Specifies the number of bits to the right of the binary point. This parameter applies
only to signed fractional buses.
Specifies the symbol width in bits.
When this option is on, the endofpacket port is available on the Avalon-ST
Source block.
When this option is on, the startofpacket port is available on the
Avalon-ST Source block.
empty port is available on the Avalon-ST Sink block.
Defines the relationship between assertion/deassertion of the Ready signal and
cycles the ones ready for data transfer separately for each interface.
When this option is on and the bit width is greater than the symbol width, the
Preliminary
Description
DSP Builder Standard Blockset Libraries
5–21