IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 300

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–14
Table 5–9. Signals Supported by the Avalon-ST Packet Format Converter Block (Part 2 of 2)
Table 5–10. Avalon-ST Packet Format Converter Block Parameters
DSP Builder Standard Blockset Libraries
inX_endofpacket
inX_startofpacket
inX_valid
outY_ready
aclr
inX_ready
outY_dataN
outY_empty
outY_endofpacket
outY_startofpacket Output
outY_valid
outYerror
Number of Sinks
Number of Sources
Split Data
Multi-Packet Mapping
Symbol Width
Use Asynchronous Clear
Port
Sink Format X
Sink X Symbols Per Beat
Source Format Y
Source Y Symbols Per Beat 1–32
Signal
Name
Table 5–10
Direction
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
1–16
1–16
On or Off
On or Off
>= 1
On or Off
string
1–32
string
Value
shows the Avalon-ST Packet Format Converter block parameters.
This signal marks the active cycle containing the end of the packet for sink
interface X.
This signal marks the active cycle containing the start of the packet for sink
interface X.
Indicates DSP Builder can accept data for sink interface X.
Indicates that the sink driven by the source interface Y is ready to accept data.
Optional asynchronous clear port.
Indicates that sink interface X is ready to output data.
Data output bus for source interface Y.
Indicates the number of empty symbols for source interface Y during cycles that
mark the end of a packet.
This signal marks the active cycle containing the end of the packet for source
interface Y.
This signal marks the active cycle containing the start of the packet for source
interface Y.
Indicates that valid data is available on source interface Y.
Indicates an error condition when asserted high.
Specifies the number of sink interfaces X.
Specifies the number of source interfaces Y.
When on, the data signals on the sink and source interface are split into signals
named data0 through dataN with widths corresponding to the specified
symbol width.
When off, one input packet is matched to one output packet and the input and
output packets must have the name number of instances in each field. When on,
the PFC maps the input packets to output packets such that all instances of every
data field are accounted for.
Specifies the number of bits per symbol that all the PFC sink and source
interfaces use.
Turn on to use the asynchronous clear input (aclr).
A quoted string or MATLAB variable that describes the packet format for sink
interface X.
Specifies the number of symbols per beat for sink interface X.
A quoted string or MATLAB variable that describes the packet format for source
interface Y.
Specifies number of symbols per beat for source interface Y.
Preliminary
Description
Description
Avalon-ST Packet Format Converter
© June 2010 Altera Corporation
Chapter 5: Interfaces Library