IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 316

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–8
Bus Conversion
Table 6–10. Bus Conversion Block Parameters
Table 6–11. Bus Conversion Block I/O Formats
DSP Builder Standard Blockset Libraries
Bus Type
Input [number of bits].[]
Input [].[number of bits]
Output [number of bits].[] >= 0
Output [].[number of bits] >= 0
Input Bit Connected to
Output LSB
Round
Saturate
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
[LPi].[RPi]
[LPO].[RPO]
Table
Simulink (2),
Name
is an input port. O1
6–11:
1
The Bus Conversion block extracts a subsection of a bus including bus type and
width conversion. If the input is in signed binary fractional format, you should
specify a left bit width (number of integer bits) and a right bit width (number of
fractional bits) for the output bus. If the input is an integer, specify the input bit to
connect to the output LSB.
If Input Bit Connected To Output LSB is on, the input bit indexing starts from 0. Do
not use this option with signed fractional type or with rounding.
Table 6–10
Table 6–11
(3)
[L].[R]
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
(Parameterizable)
(Parameterizable)
>= 0
(Parameterizable)
On or Off
On or Off
is an output port.
I1: in STD_LOGIC_VECTOR({LPi + RPi - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({LPO + LPO - 1} DOWNTO 0)
Value
shows the Bus Conversion block I/O formats.
shows the Bus Conversion block parameters.
The input bus type for the simulator, VHDL or both.
Specifies the number of bits to the left of the binary point including the
sign bit.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed binary fractional buses.
Specifies the number of bits to the left of the binary point.
Specifies the number of bit on the right side of the binary point. This
parameter applies only to signed binary fractional buses.
Specifies the slice of the input bus to use. This parameter designates the
start point of the slice that is transferred to the output LSB and applies to
signed or unsigned integer buses only.
Turn on to round the output away from zero. When this option is off, the
LSM is truncated: <int>(input +0.5).
When this option is on, if the output is greater than the maximum positive
or negative value to be represented, the output is forced (or saturated) to
the maximum positive or negative value, respectively. If off, the MSB is
truncated.
(Note 1)
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 6: IO & Bus Library
Bus Conversion
Type
Explicit
Explicit
(4)