IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 217

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Divider
Figure 2–4. Differentiator Block Example
Divider
Table 2–17. Divider Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
Bus Type
[number of bits].[]
Name
1
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
Figure 2–4
The Divider block takes a numerator and a denominator and returns the quotient
and a remainder with the equation:
q and r are undefined if b is zero.
Dividing a maximally negative number by a minimally negative one (-1 if using
signed integers), outputs a truncated answer.
The numerator and denominator inputs can have different widths but convert to the
specified bit width.
Table 2–16
Table 2–16. Divider Block Inputs and Outputs
Table 2–17
a
b
ena
aclr
q
r
a = b × q + r.
Value
Signal
shows an example with the Differentiator block.
shows the Divider block inputs and outputs.
shows the Divider block parameters.
The bus number format that you want to use for the divider.
Specify the number of bits to the left of the binary point.
Input
Input
Input
Input
Output
Output
Direction
Preliminary
Numerator.
Denominator.
Optional clock enable.
Optional asynchronous clear.
Quotient.
Remainder.
Description
Description
DSP Builder Standard Blockset Libraries
2–9