IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 197

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: AltLab Library
HDL Input
HDL Input
Table 1–8. HDL Input Block Parameters
Table 1–9. HDL Input Block I/O Formats (Part 1 of 2)
© June 2010 Altera Corporation
Bus Type
[number of bits].[]
[].[number of bits]
External Type
I
I/O
I1
Name
[L1].[R1]
Simulink (2),
Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
>= 0
(Parameterizable)
>= 0
(Parameterizable)
Inferred,
Simulink Fixed Point Type,
Double
(3)
Table 1–7. Unsupported Megafunctions and LPM Functions
Connect the HDL Input block directly to an input node in a subsystem. Use with the
Subsystem Builder
The type and bit width must match the type and bit width on the corresponding input
port in the HDL file referenced by the HDL Entity block. HDL Input blocks are
automatically generated by the
You can optionally specify the external Simulink type. If set to Simulink Fixed
Point Type, the bit width is the same as the input. If set to Double, the width may
be truncated if the bit width is greater than 52.
Table 1–8
.
Table 1–9 on page 1–7
alt3pram
altcam
altcdr
altclklock
altddio
altdpram
altera_mf_common
altfp_mult
altlvds
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
Value
shows the HDL Input block parameters.
Megafunctions
shows the HDL Input block I/O formats.
altmemmult
altmult_accum
altpll
altqpram
altsqrt
alt_exc_dpram
alt_exc_upcore
dcfifo
The number format of the bus.
Specify the number of bits to the left of the binary point, including the
sign bit. This parameter does not apply to single-bit buses.
Specify the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
Specifies whether the external type is inferred from the Simulink block it
is connected to or explicitly set to either Simulink Fixed Point or Double
type. The default is Inferred.
and
(Note 1)
HDL Entity
Preliminary
Subsystem Builder
VHDL
blocks for black-box simulation.
lpm_and
lpm_bustri
lpm_clshift
lpm_constant
lpm_decode
lpm_divide
lpm_ff
lpm_fifo
lpm_fifo_dc
Description
block.
DSP Builder Standard Blockset Libraries
LPM Functions
lpm_inv
lpm_latch
lpm_or
lpm_pad
lpm_ram_dq
lpm_ram_io
lpm_rom
lpm_shiftreg
lpm_xor
Implicit - Optional
Type
(4)
1–7