IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 265

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
Bitwise Logical Bus Operator
Table 4–3. Binary to Seven Segments Display Block I/O Formats (Part 2 of 2)
Figure 4–1. Binary to Seven Segments Block Example
Bitwise Logical Bus Operator
© June 2010 Altera Corporation
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
[7].[0]
Table
Simulink (2),
is an input port. O1
4–3:
(3)
Figure 4–1
The Bitwise Logical Bus Operator block performs bitwise AND, OR, or XOR
logical operations on two input buses.
Table 4–4
Table 4–4. Bitwise Logical Bus Operator Block Inputs and Outputs
a
b
q
[L].[R]
Signal
O1: in STD_LOGIC_VECTOR(6 DOWNTO 0)
is an output port.
shows the Bitwise Logical Bus Operator block inputs and outputs.
shows an example with the Binary to Seven Segments block.
Input
Input
Output
Direction
Preliminary
Data input a.
Data input b.
Data output.
VHDL
(Note 1)
Description
DSP Builder Standard Blockset Libraries
Explicit
Type
(4)
4–3