IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 273

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
If Statement
Table 4–18. Flipflop Block I/O Formats
Figure 4–6. Flipflop Block Example
If Statement
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
O1
[L].[R]
[L1].[0]
[1].[0]
[1].[0]
[1].[0]
[L1].[0]
Table
Simulink (2),
is an input port. O1
4–18:
Table 4–18
Figure 4–6
The If Statement block outputs a 0 or 1 result based on the IF condition
expression.
Table 4–19
Table 4–19. If Statement Block Inputs and Outputs
(3)
a–j
n
true
false
[L].[R]
Signal
is an output port.
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
I4: in STD_LOGIC
O1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
shows the Flipflop block I/O formats.
shows an example with the Flipflop block.
shows the If Statement block inputs and outputs.
(Note 1)
Input
Input
Output
Output
Direction
Preliminary
Input ports.
Optional ELSE IF input port.
Output port (high when true).
Optional ELSE output port (high when false).
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
4–11
(4)