IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 46

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–2
Using a MATLAB Variable
Fixed-Point Notation
Table 3–1. Fixed-Point Notation
DSP Builder Standard Blockset User Guide
Signed binary:
fractional (SBF)
representation; a
fractional number
Signed binary;
integer (INT)
Unsigned binary;
integer (UINT)
Description
f
1
1
[L].[R] where: [L] is the number of bits to the left of
[L] where:
[L] where:
■
■
White spaces in the names for the blocks, components, and signals are converted to an
underscore when DSP Builder converts the Simulink model file (.mdl) into VHDL.
You can specify many block parameters (such as bit widths and pipeline depth) by
entering a MATLAB base workspace or masked subsystem variable. You can then set
these variables on the MATLAB command line or from a script. DSP Builder evaluates
the variable and passes its value to the simulation model files. DSP Builder ensures
that the parameters are in the required range.
Although DSP Builder no longer restricts parameters to 51 bits, MATLAB evaluates
parameter values to doubles, which restricts the possible values to 51-bit numbers
expressible by a double.
For information about which values are parameterizable, refer to the
Standard Blockset Libraries
block descriptions, which you can access with the Help command in the right button
pop-up menu for each block.
Figure 3–1
block descriptions.
Begin all port names with a letter (a - z). VHDL does not allow identifiers to begin
with non-alphabetic characters or end with an underscore.
Do not use two underscores in succession (__) in port names because it is illegal in
VHDL.
describes the fixed-point notation that I/O formats use in the DSP Builder
the binary point and the MSB is the
sign bit
[R] is the number of bits to the right
of the binary point
[L] is the number of bits of the
signed bus and the MSB is the sign
bit
[L] is the number of bits of the
unsigned bus
Notation
section in volume 2 of the DSP Builder Handbook or to the
Preliminary
A Simulink SBF signal A[L].[R] maps in VHDL to
STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
A Simulink signed binary signal A[L] maps to
STD_LOGIC_VECTOR({L - 1} DOWNTO 0)
A Simulink unsigned binary signal A[L] maps to
STD_LOGIC_VECTOR({L - 1} DOWNTO 0)
Simulink-to-HDL Translation
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
(1),
(2)
Using a MATLAB Variable
DSP Builder