IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 81

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Using MegaCore Functions
MegaCore Function Design Example
Compiling the Design
© June 2010 Altera Corporation
Table 4–6. Configuration Parameters for the singen Model
3. Click OK.
4. On the Simulation menu in the simulink model, click Start. The scope output
Figure 4–6. Simulation Output
To create and compile a Quartus II project for your DSP Builder design, and to
program your design onto an Altera FPGA, add a Signal Compiler block. Follow
these steps:
1. Select the AltLab library from the Altera DSP Builder Blockset folder in the
2. Drag and drop a Signal Compiler block into your model.
3. Double-click the new Signal Compiler block in your model. The Signal
Parameter
Start time
Stop time
Type
Solver
f
shows the effect of the low-pass filter in the bottom window
Check that the FIR filter block behaves as you expect and filters high-frequency
data as a low-pass filter.
1
Simulink Library Browser.
Compiler dialog box appears
You may need to use the Autoscale command in the Scope display to view
the complete waveforms.
For detailed information about solver options, refer to the description of
the Solver Pane in the Simulink Help.
Preliminary
(Figure
4–7).
Value
0.0
5000
Fixed-step
discrete (no continuous states)
DSP Builder Standard Blockset User Guide
(Figure
4–6).
4–9