IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 131

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Implicit Black Box Interface
Explicit Black-Box Interface
HDL Import Design Example
© June 2010 Altera Corporation
f
f
1
The Signal Compiler block converts subsystems with blocks from the DSP Builder
block libraries into HDL code. Non-DSP Builder blocks, such as encapsulations of
your own pre-existing HDL code, require the Signal Compiler block to recognize
them as black boxes so that the conversion process does not alter them.
There are two types of black-box interface in DSP Builder: implicit and explicit.
Use the HDL Import block to infer the implicit black-box interface.
The Signal Compiler block recognizes the HDL Import block as a black box and
bypasses this block during the HDL translation.
For information about the HDL Import block, refer to the block description in the
AltLab Library chapter of the
of the DSP Builder Handbook.
Use the HDL Input, HDL Output, HDL Entity, and Subsystem Builder blocks
to specify the explicit black-box interface.
Using the HDL Input, HDL Output, and HDL Entity blocks prevents Signal
Compiler from translating the subsystem into HDL. You can also use a Subsystem
Builder block to create a new subsystem and then automatically populate its ports
using the specified HDL.
Typically use the explicit black-box interface to encapsulate non-DSP Builder blocks
from the main Simulink blocksets.
For information about the HDL Input, HDL Output, HDL Entity, and Subsystem
Builder blocks, refer to the block descriptions in the AltLab Library chapter of the
DSP Builder Standard Blockset Libraries
Handbook.
The HDL Import block provides an interface to import a HDL module into your DSP
Builder design.
To define imported VHDL use std_logic_1164 types. If your design uses any other
VHDL type definitions (such as arithmetic or numeric types), write a wrapper that
converts them to std_logic or std_logic_vector.
The following sections show an example of importing an existing VHDL design into
the DSP Builder environment with the HDL Import block.
8. Using Black Boxes for HDL Subsystems
DSP Builder Standard Blockset Libraries
Preliminary
section in volume 2 of the DSP Builder
DSP Builder Standard Blockset User Guide
section in volume 2