IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 246

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–38
Table 2–58. Sum of Products Block I/O Formats
Figure 2–22. Sum of Product Block Example
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
...
In
I(n+1)
I(n+2)
O1
1))].[2R]
Simulink (2),
[L].[R]
[L].[0]
[L].[0]
[2L + cell(log2(n +
Table
is an input port. O1
2–58:
(3)
Figure 2–22
I1: in STD_LOGIC_VECTOR({L - 1} DOWNTO 0)
...
In: in STD_LOGIC_VECTOR({L - 1} DOWNTO 0)
I(n+1): STD_LOGIC
I(n+2): STD_LOGIC
O1: out STD_LOGIC_VECTOR({2L + cell(log2(n + 1)) + 2R - 1} DOWNTO 0) Explicit
[L].[R]
is an output port.
shows an example with the Sum of Product block.
(Note 1)
Preliminary
VHDL
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
...
Explicit
Type
Sum of Products
(4)