IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 400

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

13–4
Switch Control
Avalon-MM Interface
Avalon-MM FIFO
DSP Builder Standard Blockset Libraries
f
f
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1
This design example shows how you can use blocks to control the switches on a DSP
Development board and how to perform the SignalTap II analysis in DSP Builder.
The example model is switch_control.mdl.
For more information about this design, refer to the SignalTap II Design Example in the
Performing SignalTap II Logic Analysis chapter in the
Guide
This example consists of a 4-tap FIR filter with variable coefficients. The coefficients
load with an Avalon-MM write slave while an off-chip source supplies the input data
through an analog-to-digital converter. The design example sends filtered output data
off-chip through a digital-to-analog converter. You can include the design as an SOPC
Builder peripheral to the Avalon-MM bus.
The example model is topavalon.mdl.
For more information about this design, refer to the Avalon-MM Interface Blocks in the
Using the Interfaces Library chapter in the
section in volume 2 of the DSP Builder Handbook.
The design example uses a Stratix II EP2S60 DSP development board but you can
configure the design for other boards (for example, the Cyclone II EP2C35
development board). Altera provide alternative design examples in the CII and SII
subdirectories under the <DSP Builder install
path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\Finished Examples
directory.
This design example consists of a Prewitt edge detector with one Avalon-MM Write
FIFO buffer and one Avalon-MM Read FIFO buffer. DSP Bu idler uses an additional
slave port as a control port. You can include the design as an SOPC Builder peripheral
to the Avalon-MM bus.
The example model is sopc_edge_detector.mdl.
For more information about this design, refer to Avalon-MM FIFO Buffer in the Using
the Interfaces Library chapter in the
volume 2 of the DSP Builder Handbook.
section in volume 2 of the DSP Builder Handbook.
Preliminary
DSP Builder Standard Blockset User Guide
DSP Builder Standard Blockset User Guide
DSP Builder Standard Blockset User
© June 2010 Altera Corporation
Chapter 13: Design Examples
section in
Switch Control