IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 115

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 7: Using the Interfaces Library
Avalon-MM Interface Blocks
Figure 7–4. Avalon-MM Write FIFO Content
© June 2010 Altera Corporation
Figure 7–4
The Avalon-MM Write Test Converter block handles caching and conversion of
Simulink or MATLAB data into accesses over the Avalon-MM interface. You can use
this block to test the functionality of your design. The Avalon-MM Write Test
Converter is simulation only and does not synthesize to HDL.
Avalon-MM Read FIFO Buffer
An Avalon-MM read FIFO buffer has the following ports:
■
■
■
■
■
■
Double-clicking on an Avalon-MM Write FIFO block opens the Block Parameters
dialog box that you can use to set parameters for the data type, data width and FIFO
depth.
You can open the hierarchy below the Avalon-MM Read FIFO block by
right-clicking on the block and choosing Look Under Mask from the pop-up menu.
Figure 7–5
Stall (input). Connect this port to a Simulink block. It simulates stall conditions
of the Avalon-MM bus and hence backpressure to the SOPC Builder component.
For any simulation cycle where Stall asserts, no Avalon-MM reads take place
and the internal FIFO buffer fills. When full, the Ready output is de-asserted so
that you lose no data.
Data (input). Connect this port to a DSP Builder block and to outgoing data from
the user design.
DataValid (input). Connect this port to a DSP Builder block and assert whenever
the signal on the Data port corresponds to real data.
TestDataOut (output). Connect this port to a Simulink block that corresponds to
data received over the Avalon-MM bus.
TestDataValid (output). Connect this port to a Simulink block and assert
whenever TestDataOut corresponds to real data.
Ready (output). When asserted, indicates that the block is ready to receive data.
shows the internal content of an Avalon-MM Write FIFO buffer.
shows the internal content of an Avalon-MM Read FIFO.
Preliminary
DSP Builder Standard Blockset User Guide
7–7