IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 343

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Down Sampling
Table 9–3. Delay Block I/O Formats (Part 2 of 2)
Figure 9–1. Delay Block Example
Down Sampling
Table 9–5. Down Sampling Block Parameters
© June 2010 Altera Corporation
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
Down Sampling Rate
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
Name
[L1].[R1]
Table
Simulink (2),
is an input port. O1
9–3:
Figure 9–1
The Down Sampling block decreases the output sample rate from the input sample
rate. The output data is sampled at every Nth cycle where N is the down sampling
rate. The output data is then held constant for the next N input cycles.
Table 9–4
Table 9–4. Down Sampling Block Inputs and Outputs
Table 9–5
(3)
d
q
An integer greater than 1
(Parameterizable)
[L].[R]
Signal
is an output port.
O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
Value
shows the Down Sampling block inputs and outputs.
shows the Down Sampling block parameters.
shows an example with the Delay block.
Input
Output
Direction
(Note 1)
Specify the down sampling rate.
Preliminary
Input data port.
Output data port.
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Type
Implicit
(4)
9–3