IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 327

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Round
Table 6–30. Round Block Parameters (Part 2 of 2)
Table 6–31. Round Block I/O Formats
Figure 6–12. Round Block Example
© June 2010 Altera Corporation
Rounding Mode
Enable Pipeline
Use Enable Port
Use Asynchronous
Clear Port
Note to
(1) These ports are available only when you enable pipeline.
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
[L].[R]
Name
Table
[L1].[R1]
[1]
[1]
[LP].[RP]
Table
Simulink (2),
(1)
is an input port. O1
6–30:
6–31:
(1)
Truncate,
Round Towards Zero,
Round Away From Zero,
Round To Plus Infinity,
Convergent Rounding
On or Off
On or Off
On or Off
Table 6–31
Figure 6–12
(3)
[L].[R]
Value
is an output port.
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
shows the Round block I/O formats.
shows a design example with the Round block.
(Note 1)
The rounding mode.
Turn on if you want to pipeline the function.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
6–19
(4)