IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 277

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
LFSR Sequence
Figure 4–9. Internal 2-Input Gate Circuitry
Table 4–24. LFSR Sequence Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
LFSR Length
Feedback Structure
Feedback Gate Type
Initial Register Value
(Hex)
Primitive Polynomial
Tap Sequence
Specify Clock
Clock
Use Parallel Output
Name
On or Off
For example, after changing the feedback structure to an internal two-inputs gate,
DSP Builder implements the circuitry
This circuitry changes the sequence from:
to:
Table 4–23
Table 4–23. LFSR Sequence Block Inputs and Outputs
Table 4–24
User Defined
(Parameterizable)
External n-inputs gate,
Internal two-inputs gate
XOR or XNOR
Any Hexadecimal Number
(Parameterizable)
User-Defined Array of
Polynomial Coefficients
(Parameterizable)
On or Off
User defined
(Parameterizable)
ena
rst
sout
pout
1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1
1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0
Signal
Value
shows the LFSR Sequence block inputs and outputs.
shows the LFSR Sequence block parameters.
Input
Input
Output
Output
Direction
Specify the LFSR length as an integer.
Specify whether you want an external n-inputs gate (many-to-one) or
internal two-inputs gate (one-to-many) structure.
Specify the type of feedback gate to implement.
Specify the initial values in the register. If this value is larger than is
represented in the shift register (set by LFSR Length) the
unrepresentable bits are truncated.
Specify where the taps occur in the shift register, 1 denotes the LSB and
the LFSR length denotes the MSB. There must be a minimum of 2 taps.
The numbers should be enclosed in square brackets.
For example, [0 3 10].
Turn on to explicitly specify the clock name.
Specify the name of the clock signal.
Turn on to use the parallel output (pout).
Preliminary
Optional clock enable port.
Optional reset port.
Serial output port for MSB of the LFSR.
Optional parallel output port for LFSR unsigned value.
(Figure
4–9).
Description
Description
DSP Builder Standard Blockset Libraries
4–15