IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 261

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Complex Type Library
Real-Imag to Complex
Table 3–25. Real-Imag to Complex Block Parameters
Table 3–26. Real-Imag to Complex Block I/O Formats
Figure 3–9. Real-Imag to Complex Block Example
© June 2010 Altera Corporation
Bus Type
[number of bits].[]
[].[number of bits]
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
O1
[L].[R]
Real([L1].[R1])
Imag([L1].[R1])
Real([L1].[R1])Imag([L1].[R1])
Table
Name
Simulink (2),
is an input port. O1
3–26:
Table 3–25
Table 3–26
Figure 3–9
(3)
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
[L].[R]
is an output port.
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
Value
shows the Real-Imag to Complex block parameters.
shows the Real-Imag to Complex block I/O formats.
shows an example with the Real-Imag to Complex block.
Specify the number format you want to use for the bus.
Select the number of data input bits to the left of the binary point, including
the sign bit.
Select the number of data input bits to the right of the binary point. This
option applies only to signed fractional formats.
(Note 1)
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Implicit
Explicit
3–15
(4)