IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 368

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–28
Up Sampling
Table 9–41. Up Sampling Block I/O Formats
Figure 9–14. Up Sampling Block Example
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
[L1].[R1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
9–41:
The Up Sampling block increases the output sample rate from the input sample rate.
The output data is sampled every N cycles where N is equal to the up sampling rate.
The output holds this value for 1 cycle, then for the next N-1 cycles the output is zero.
Table 9–39
Table 9–39. Up Sampling Block Inputs and Outputs
Table 9–40
Table 9–40. Up Sampling Block Parameter
Table 9–41
Figure 9–14
(3)
d
q
Up Sampling Rate An integer greater than 1
[L].[R]
Signal
Name
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
shows the Up Sampling block inputs and outputs.
shows the Up Sampling block parameter.
shows the Up Sampling block I/O formats.
shows an example with the Up Sampling block.
Input
Output
(Parameterizable)
Direction
(Note 1)
Value
Preliminary
Input data port.
Output data port.
VHDL
Specify the up sampling rate.
Description
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
Up Sampling
Type
Implicit
Implicit
(4)