IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 293

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Interfaces Library
Avalon-MM Slave
Table 5–4. Avalon-MM Slave Block Parameters
© June 2010 Altera Corporation
Specify Clock
Clock
Address Width
Address Alignment
Address Type
Data Type
[number of bits].[]
[].[number of bits]
Allow Byte Enable
Allow Flow Control
Allow Pipeline
Transfers
Wait-State Format
Read Wait-State Cycles 0–255
Write Wait-State Cycles 0–255
Read Latency Format
Read Latency Cycles
Allow Burst Transfers
Maximum Burst Size
Output IRQ
Receive BeginTransfer
Use Chip Select
Name
On or Off
User defined
1–32
Native, Dynamic
Read, Write,
Read/Write
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
On or Off
On or Off
Fixed, Variable
Fixed, Variable
0–8
On or Off
4–2
On or Off
On or Off
On or Off
32
Value
Turn on to explicitly specify the clock name.
Specifies the clock signal name.
Specifies the number of address bits.
Use native address alignment or dynamic bus sizing.
The address type for the bus.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign
bit. Read and write buses must have the same number of bits.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
Turn on to use the Byte Enable signal. This option is available only when
the address type is set to Write or Read/Write.
Turn on to enable flow control. Flow control allows a slave port to regulate
incoming transfers from a master port, so that a transfer only begins when
the slave port indicates that it has valid data or is ready to receive data.
Turn on to allow pipeline transfers. Pipeline transfers increase the bandwidth
for synchronous slave peripherals that require several cycles to return data
for the first access, but can return data every cycle thereafter. This option is
available only when the address type is set to Read or Read/Write.
The required wait-state format.
Specifies the number of read wait-state cycles. This option is available only
when the wait-state format is set to Fixed.
Specifies the number of write wait state cycles. This option is available only
when the wait-state format is set to Fixed.
The required read latency format. This option is available only when Allow
Pipeline Transfers is on.
Specifies the pipeline read latency. Latency determines the length of the data
phase, independently of the address phase. For example, a pipelined slave
port (with no wait-states) can sustain one transfer per cycle, even though it
may require several cycles of latency to return the first unit of data. This
option is available only when Allow Pipeline Transfers is on and Fixed read
latency format is set.
Turn on to allow burst transfers. A burst executes multiple transfers as a unit,
and maximize the throughput for slave ports that achieves the greatest
efficiency when handling multiple units of data from one master port at a
time.
Specifies the maximum width of a burst transfer. This option is available only
when Allow Burst Transfer is on.
Turn on to enable interrupt requests from the slave port.
Turn on to receive begintransfer signals.
Turn on to enable the chipselect signal.
Preliminary
Description
DSP Builder Standard Blockset Libraries
5–7