IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 323

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Non-synthesizable Input
Table 6–23. Input Block I/O Formats
Non-synthesizable Input
Table 6–24. Non-synthesizable Input Block Parameters
Table 6–25. Non-synthesizable Input Block I/O Formats
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Specify Clock
Clock
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
I1
O1
[L].[R]
[L].[R]
Name
[L1].[R1]
[L1].[R1]
Simulink (2),
Simulink (2),
[LP].[RP]
Table
[LP].[RP]
Table
is an input port. O1
is an input port. O1
6–23:
6–23:
Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
(Parameterizable)
(Parameterizable)
On or Off
User defined
(Parameterizable)
(3)
(3)
The Non-synthesizable Input block marks an entry point to a non-synthesizable
DSP Builder system. Use a corresponding
mark the exit point. Because DSP Builder registers its own type with Simulink, this
block is required when the DSP Builder blocks are not intended to be synthesized.
Table 6–24
Table 6–25
[L].[R]
[L].[R]
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
Value
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
is an output port.
is an output port.
shows the Non-synthesizable Input block parameters.
shows the Non-synthesizable Input block I/O formats.
(Note 1)
Specifies the number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
Turn on to explicitly specify the clock name.
Specifies the name of the required clock signal.
Preliminary
(Note 1)
VHDL
VHDL
Non-synthesizable Output
Description
DSP Builder Standard Blockset Libraries
Implicit - Optional
Implicit - Optional
Explicit
Explicit
Type
Type
block to
(4)
(4)
6–15