IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 91

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Using HIL
HIL Design Example
HIL Design Example
Figure 5–2. Frequency Sweep Model
© June 2010 Altera Corporation
1
DSP Builder includes the following design examples in the <DSP Builder install
path>\DesignExamples\Tutorials\HIL directory that demonstrate the use and
effectiveness of HIL:
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This section shows the frequency sweep design.
This tutorial uses the Stratix II hardware device on an Altera Stratix II EP2S60 DSP
Development Board. However, you can also use any other supported device and
development board.
To create a frequency sweep design, follow these steps:
1. Run MATLAB, and open the model FreqSweep.mdl in the <DSP Builder install
2. Double-click the Signal Compiler block. In the dialog box that appears
Imaging edge detection
Export example
Fast Fourier Transform (FFT)
Frequency sweep
path>\DesignExamples\Tutorials\HIL\FreqSweep directory.
the model.
(Figure 5–3 on page
This action creates a Quartus II project, FreqSweep.qpf, compiles your model for
synthesis, and runs the Quartus II Fitter.
Progress is indicated by status messages and a scrolling bar at the bottom of the
dialog box.
5–4), click Compile.
Preliminary
DSP Builder Standard Blockset User Guide
Figure 5–2
shows
5–3