IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 353

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Memory Delay
Figure 9–6. LUT Block Example
Memory Delay
Table 9–19. Memory Delay Block Parameters
© June 2010 Altera Corporation
Data Type
[number of bits].[]
[].[number of bits]
Number of Pipeline Stages
Memory Block Type
Use Enable Port
Use Synchronous Clear Port On or Off
Name
Figure 9–6
The Memory Delay block implements a shift register that uses the Altera device’s
embedded memory blocks, when possible. You should typically use this block for
delays greater than 3.
Table 9–21
Table 9–18. Memory Delay Block Inputs and Outputs
Table 9–19
d
ena
sclr
q
Signal
Inferred,
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
0 to number of bits
(Parameterizable)
AUTO, M512, M4K,
M9K, MLAB, M144K
On or Off
shows an example with the LUT block.
shows the Memory Delay block inputs and outputs.
shows the Memory Delay block parameters.
Value
Input
Input
Input
Output
Direction
The data type format that you want to use.
Specify the number of data bits stored on the left side of the binary
point including the sign bit.
Specify the number of data bits stored on the right side of the binary
point.
When non-zero, adds pipeline stages to increase the data throughput.
The clock enable and synchronous clear ports are available only if the
block is registered (that is, if the number of pipeline stages is greater
than or equal to 1).
The RAM block type. Some memory types are not available for all
device types.
Turn on to use the clock enable input.
Turn on to use the synchronous clear port (sclr).
Preliminary
Input data port.
Optional clock enable port.
Optional synchronous clear port.
Output data port.
Description
Description
DSP Builder Standard Blockset Libraries
9–13