IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 132

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–2
Importing Existing HDL Files
DSP Builder Standard Blockset User Guide
To import existing HDL files into a DSP Builder design, follow these steps:
1. In MATLAB, change the current directory setting to: <DSP Builder install
2. On the File menu, click Open and select empty_MyFilter.mdl.
3. Rename the file by clicking Save As on the File menu. Name your new MDL file
4. Open the Simulink Library Browser. Expand the Altera DSP Builder Blockset and
5. Drag and drop a HDL Import block into your model.
6. Double-click on the HDL Import block to bring up the DSP Builder HDL Import
7. In the HDL Import dialog box, enable the Import HDL radio button and click on
8. From the VHDL Black Box File dialog box, select the files fir_vhdl.vhd,
9. Ensure that fir_vhdl is specified as the name of the top-level design entity. The
path>\DesignExamples\Tutorials\BlackBox\HDLImport
This design file has some of the peripheral blocks instantiated including the input
and output ports and source blocks that provide appropriate stimulus for
simulation. It is missing the main filter function, which you can import as HDL.
MyFilter.mdl.
select the AltLab library.
dialog box
the Add button to select the HDL input files.
four_mult_add.vhd, and final_add.vhd, then click on Open.
fir_vhdl.vhd file describes the top-level entity, which implements an 8-tap
low-pass FIR filter design.
(Figure 8–1 on page
Preliminary
8–3).
Chapter 8: Using Black Boxes for HDL Subsystems
© June 2010 Altera Corporation
HDL Import Design Example