IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 268

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–6
Table 4–9. Case Statement Block I/O Formats (Part 2 of 2)
Figure 4–3. Case Statement Block Example
DSP Builder Standard Blockset Libraries
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1[
…
Oi
….
On
[L].[R]
[1]
[1]
Table
Simulink (2),
1]
is an input port. O1
4–9:
(3)
Figure 4–3
The following VHDL code generates from the model in
caseproc:process( input )
[L].[R]
begin
O1: out STD_LOGIC
…
Oi: out STD_LOGIC
….
On: out STD_LOGIC
is an output port.
case input is
shows an example model with the Case Statement block.
when "00000001" | "00000010" | "00000011" =>
when "00000100" =>
when "00000100" | "00000110" =>
r0 <= '1';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '0';
r0 <= '0';
r1 <= '1';
r2 <= '0';
r3 <= '0';
r4 <= '0';
r0 <= '0';
Preliminary
(Note 1)
VHDL
Figure
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
4–3:
Case Statement
Type
Explicit
(4)