IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 260

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–14
Table 3–23. Complex to Real-Imag Block I/O Formats
Figure 3–8. Complex to Real-Imag Block Example
Real-Imag to Complex
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
O2
[L].[R]
Real([L1].[R1])Imag([L1].[R1])
Real([L1].[R1])
Imag([L1].[R1])
Table
Simulink (2),
is an input port. O1
3–23:
Table 3–23
Figure 3–8
The Real-Imag to Complex block constructs a fixed-point complex output from
real and imaginary inputs.
Table 3–24
Table 3–24. Real-Imag to Complex Block Inputs and Outputs
(3)
r
i
c
[L].[R]
Signal
is an output port.
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
O2Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
shows the Complex to Real-Imag block I/O formats.
shows an example with the Complex to Real-Imag block.
shows the Real-Imag to Complex block has the inputs and outputs.
Input
Input
Output
Direction
(Note 1)
Preliminary
Real part input.
Imaginary part input.
Complex output.
VHDL
Description
Chapter 3: Complex Type Library
© June 2010 Altera Corporation
Real-Imag to Complex
Type
Implicit
Explicit
(4)