IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 124

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7–16
Avalon-MM FIFO Design Example
Opening the Design Example
DSP Builder Standard Blockset User Guide
f
f
1
For information about using SOPC Builder to create a custom Nios II embedded
processor, refer to
Completed versions of the topavalon.mdl design for the Cyclone II EP2C35 and
Stratix II EP2S60 DSP development boards are available in the <DSP Builder install
path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\Finished Examples
directory.
This tutorial describes how to interface a design built using the Avalon-MM FIFO
block as a custom peripheral to the Nios
The design consists of a Prewitt edge detector with one Avalon-MM write FIFO buffer
and one Avalon-MM read FIFO buffer. The design uses an additional slave port as a
control port.
For a full description of the Prewitt edge detector design, refer to
Detection Reference
For this hardware implementation, DSP Builder stores the image in the compact flash
and loads it in DMA with a Nios II embedded processor. DSP Builder outputs the
edge detected image through a VGA controller. The DSP Builder model uses Simulink
to read in the original image and to capture the edge detected result.
To open the design example, follow these steps:
1. Click Open on the File menu in the MATLAB software.
2. Browse to the <DSP Builder install path>\DesignExamples\Tutorials\
3. Select the sopc_edge_detector.mdl file and click Open.
Figure 7–10
Coefficient 2 = 0
Coefficient 3 = 0
Coefficient 4 = 0
RELOADING...
Coefficient 1 = 0
Coefficient 2 = 0
Coefficient 3 = 1
Coefficient 4 = 0
SOPCBuilder\AvalonFIFO directory.
shows sopc_edge_detector.mdl.
AN 351: Simulating Nios II Embedded Processor
Design.
Preliminary
®
II embedded processor in SOPC Builder.
Chapter 7: Using the Interfaces Library
© June 2010 Altera Corporation
Avalon-MM FIFO Design Example
Designs.
AN364: Edge