IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 267

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
Case Statement
Case Statement
Table 4–8. Case Statement Block Parameters
Table 4–9. Case Statement Block I/O Formats (Part 1 of 2)
© June 2010 Altera Corporation
Case Statement
Data Bus Type
[number of bits].[]
[].[number of bits]
Enable Pipeline
Provide Default Case On or Off
I
I/O
I1[
Name
L1].[R1]
Simulink (2),
(3)
This Case Statement block contains boolean operators, which you can use for
combinational functions.
The Case Statement block compares the input signal (which must be a signed or
unsigned integer) with a set of values (or cases). A single-bit output generates for each
case. You can implement multiple cases with a comma (,) to separate each case. A
comma at the end of the case values is ignored.
You can have multiple conditions for each case with a pipe (|) to separate the
conditions. For example, for four cases if the first has two conditions, enter
1|2,3,4,5 in the Case Values box.
Table 4–7
Table 4–7. Case Statement Block Inputs and Outputs
Table 4–8
User defined
(Parameterizable)
Signed Integer,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
Table 4–9
unnamed
0 to n
Value
Signal
I1: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
shows the Case Statement block inputs and outputs.
shows the Case Statement block parameters.
shows the Case Statement block I/O formats.
Specify the values with which you want to compare the input. Use a comma
between each case and separate conditions by a pipe (|). For example:
1|2|3,4,5|-1,7
Specify the bus number format that you want to use.
Specify the number of bits to the left of the binary point, including the sign bit.
Specify the number of bits to the right of the binary point.
Turn on if you want pipeline the output result.
Turn on if you want the others output signal to go high when all the other
outputs are false.
Input
Output
Direction
Preliminary
Data input.
A separate output is provided for each case.
(Note 1)
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
(4)
4–5