IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 205

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: AltLab Library
SignalTap II Node
Figure 1–5. Example SignalTap II Analysis Model
SignalTap II Node
Subsystem Builder
© June 2010 Altera Corporation
f
Figure 1–5
SignalTap II Logic Analyzer block.
Use the SignalTap II Node block with the
block to capture signal activity from internal Altera device nodes while the system
under test runs at speed. The SignalTap II Node block specifies the signals (also
called nodes) for which you want to capture activity.
The SignalTap II Node block has no parameters.
For an example of a design with the SignalTap II Logic Node block, refer to the
description of the
Refer to the Performing SignalTap II Logic Analysis chapter in the
Blockset User Guide
The Subsystem Builder block allows you to build black-box subsystems that
synthesize user-supplied VHDL and simulate non-DSP Builder Simulink blocks. This
alternative to HDL import gives better simulation speed. You can also use this block if
you cannot use HDL import because of unsupported megafunctions or LPMs.
The subsystem connects the inputs and outputs in the specified VHDL to HDL Input
and HDL Output blocks and creates an HDL Entity block, which you can modify if
the clock and reset signals are not correctly identified.
shows an example with the SignalTap II Node block and the
SignalTap II Logic Analyzer
section in volume 2 of the DSP Builder Handbook.
Preliminary
SignalTap II Logic Analyzer
block.
DSP Builder Standard Blockset Libraries
DSP Builder Standard
1–15