MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 86

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Figure 48:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
COMMAND
b.
c. At least two Auto Refresh commands are performed during each
ADDR
DQS
CK#
CKE
CK
t
Refresh mode.
DM
DQ
XSNR and
1
2
t
RP
t
t
4
IS
IS
NOP
Self Refresh Mode
T0
Enter Self Refresh Mode
t
t
t
XSRD are not violated.
IH
IH
t
CH
Notes: 1. Clock must be stable until after the self refresh command has been registered. A change in
a. The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting.
t
CL
t
IS
T1
AR
1
2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command.
3. Auto Refresh is not required at this point, but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5.
6.
7. As a general rule, any time Self Refresh Mode is exited, the DRAM may not re-enter the
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon
9. Once initialized, inclding during self refresh mode, V
clock frequency is allowed before Ta0, provided it is within the specified
Regardless, the clock must be stable before exiting self refresh mode. That is, the clock
must be cycling within specifications by Ta0.
t
DESELECT commands are allowed until Tb1.
t
be applied.
Self Refresh Mode until all rows have been refreshed via the Auto Refresh command at the
distributed refresh rate,
Refresh Mode may be re-entered anytime after exiting, if the following conditions are all
met:
exit.
fied range.
XSNR is required before any non-READ command can be applied. That is only NOP or
XSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can
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Ta0
1
Exit Self Refresh Mode
t
t CK
REFI, or faster. However, the following exception is allowed. Self
86
t IS
NOP
Ta1
t XSNR
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
XSRD
t
REFI interval while the DRAM remains out of Self
5
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7
Ta2
NOP
128Mb: x4, x8, x16 DDR SDRAM
REF
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must always be powered within speci-
t
VALID 3
IS
VALID
Tb1
t
IH
©2000 Micron Technology, Inc. All rights reserved.
Timing Diagrams
VALID
Tb2
VALID
t
CK limits.
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DON’T CARE
VALID
VALID
Tc1