MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 49

IC DDR SDRAM 128MBIT 6NS 66TSOP

MT46V32M4TG-6T:D TR

Manufacturer Part Number
MT46V32M4TG-6T:D TR
Description
IC DDR SDRAM 128MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT46V32M4TG-6T:D TR

Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (32Mx4)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1024-2
Table 10:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
CKE
H
H
L
L
n-1
CKE
H
H
L
L
Truth Table – CKE
Notes: 1-6
n
Current State
Bank(s) Active
All Banks Idle
All Banks Idle
Power-Down
Power-Down
Self Refresh
Self Refresh
Notes: 1. CKE
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop low during a column access. For a READ, this means CKE must stay high
6. Once initialized, including during self refresh mode, V
7. Upon exit of the Self Refresh mode the DLL is automatically enabled. A minimum of 200
clock edge.
MAND
until after the Read Postamble time; for a WRITE, CKE must stay high until the WRITE
Recovery Time (
specified range.
clock cycles with CKE HIGH is needed before applying a READ command for the DLL to
lock. DESELECT or NOP commands should be issued on any clock edges occurring during
the
n
t
XSNR period.
is the logic state of CKE at clock edge n; CKE
n
.
See Table 11 on page 50
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
n
AUTO REFRESH
is the command registered at clock edge n, and ACTION
Command
t
WR) has been met.
X
X
n
49
Action
Maintain Power-Down
Maintain Self Refresh
Exit Power-Down
Exit Self Refresh
Precharge Power-Down Entry
Active Power-Down Entry
Self Refresh Entry
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
128Mb: x4, x8, x16 DDR SDRAM
n-1
was the state of CKE at the previous
REF
must be powered with in the
©2000 Micron Technology, Inc. All rights reserved.
n
is a result of COM-
Operations
Notes
7

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