MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 50

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Table 11:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
Any
Idle
Row
Active
Read
(Auto-
Precharge
Disabled)
Write
(Auto-
Precharge
Disabled)
Current
• Idle: The bank has been precharged, and
• Row Active: A row in the bank has been activated, and
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
• Precharging: Starts with registration of a PRECHARGE command and ends when
• Row Activating: Starts with registration of an ACTIVE command and ends when
• Read w/Auto-Precharge Enabled: Starts with registration of a READ command with auto precharge enabled
• Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when
State
register accesses are in progress.
minated.
minated.
the bank will be in the idle state.
met, the bank will be in the “row active” state.
and ends when
and ends when
met, the DDR SDRAM will be in the all banks idle state.
CS# RAS# CAS#
Truth Table – Current State Bank n - Command to Bank n
(Notes: 1-6; notes appear below and on next page)
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
Notes: 1. This table applies when CKE
t
t
RP has been met. Once
RP has been met. Once
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank.
5. The following states must not be interrupted by any executable command; DESELECT or
after
and the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
DESELECT or NOP commands, or allowable commands to the other bank should be issued
on any clock edge occurring during these states. Allowable commands to the other bank
are determined by its current state and Table 11, Truth Table – Current State Bank n - Com-
mand to Bank n, on page 50 and according to Table 12, Truth Table – Current State Bank n
- Command to Bank m, on page 52.
NOP commands must be applied on each positive clock edge during these states.
WE#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
t
XSNR has been met (if the previous state was self refresh).
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
t
t
RP is met, the bank will be in the idle state.
RP is met, the bank will be in the idle state.
t
RP has been met.
50
n-1
t
was HIGH and CKE
RCD has been met. No data bursts/accesses and no
Command/Action
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
n
is HIGH (see Table 10 on page 49) and
t
RCD is met. Once
t
RP is met. Once
©2000 Micron Technology, Inc. All rights reserved.
t
RFC is met. Once
Operations
t
RP is met,
t
RCD is
Notes
10, 12
10, 11
8, 11
10
10
10
10
t
7
7
8
8
9
RFC is