MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 53

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Table 13:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
b. The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is
summarized below.
Minimum Delay Summary
CL
RU
= CAS Latency (CL) rounded up to the next integer BL = Bust Length
This device supports concurrent auto precharge such that when a read with auto precharge is
enabled or a write with auto precharge is enabled any command to other banks is allowed, as
long as that command does not interrupt the read or write data transfer already in process. In
either case, all other related limitations apply (e.g., contention between read data and write data
must be avoided).
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
From Command
are idle.
represented by the current state only.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
WRITE w/AP
READ w/AP
READ or READ w/AP
READ or READ w/AP
WRITE or WRITE w/
WRITE or WRITE w/
To Command
PRECHARGE
PRECHARGE
ACTIVE
ACTIVE
53
AP
AP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
(with Concurrent Auto Precharge)
[1 + (BL/2)] *
[CL
Minimum Delay
RU
(BL/2) *
(BL/2) *
+
©2000 Micron Technology, Inc. All rights reserved.
1
1
1
1
(BL/2)] *
t
t
t
t
CK
CK
CK
CK
t
CK +
t
t
CK
CK
t
CK
t
WTR
Operations