MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 23

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Auto Precharge
BURST TERMINATE
AUTO REFRESH
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
any other timing parameters. Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1
select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command will be treated as a NOP
if there is no open row in that bank (idle state), or if the previously open row is already in
the process of precharging.
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the READ or WRITE burst. Auto
precharge is nonpersistent in that it is either enabled or disabled for each individual
Read or Write command. This device supports concurrent auto precharge if the com-
mand to the other bank does not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating
each burst type in the Operation section of this data sheet. The user must not issue
another command to the same bank until the precharge time (
The BURST TERMINATE command is used to truncate read bursts (with auto precharge
disabled). The most recently registered READ command prior to the BURST TERMI-
NATE command will be truncated, as shown in the Operation section of this data sheet.
The open page which the READ burst was terminated from remains open.
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous
to CAS#-BEFORE-RAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All banks must be idle before
an AUTO REFRESH command is issued.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 128Mb DDR SDRAM
requires AUTO REFRESH cycles at an average interval of 15.625µs (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 x 15.625µs (140.6µs). Note the JEDEC specifications only allows 8 x
15.625µs, thus the Micron specification exceeds the JEDEC requirement by one clock.
This maximum absolute interval is to allow future support for DLL updates internal to
the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive
drift in
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered and ends
t
AC between updates.
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
t
RAS (MIN), as described for
©2000 Micron Technology, Inc. All rights reserved.
t
RP) is completed.
t
RFC later.
Commands