MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 36

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Figure 20:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
WRITE Command
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst,
on page 41.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 26 on page 42.
Note that only the data-in pairs that are registered prior to the
to the internal array, and any subsequent data-in should be masked with DM as shown
in Figure 27 on page 43.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst,
Figure 28 on page 44.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 29 on page 45 and Figure 30 on page 46. Note that only the data-in pairs
that are registered prior to the
sequent data-in should be masked with DM as shown in Figures 29 and 30. After the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until
x4: A0–A9, A11
DON’T CARE
x16: A9, A11
t
RP is met.
x16: A0–A8
x8: A0–A9
BA0,1
CAS#
RAS#
WE#
x8: A11
A10
CKE
CK#
CS#
CK
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
HIGH
DIS AP
EN AP
CA
BA
36
t
WR period are written to the internal array, and any sub-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WTR should be met as shown in Figure 25
128Mb: x4, x8, x16 DDR SDRAM
t
WR should be met as shown in
©2000 Micron Technology, Inc. All rights reserved.
t
WTR period are written
Operations