MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 19

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Operating Mode
Extended Mode Register
Output Drive Strength
DLL Enable/Disable
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
The normal operating mode is selected by issuing a MODE REGISTER SET command
with bits A7-A11 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 each set
to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required
by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER
command is issued to reset the DLL, it should always be followed by a LOAD MODE
REGISTER command to select normal operating mode.
All other combinations of values for A7-A11 are reserved for future use and/or test
modes. Test modes and reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, and output drive strength.
These functions are controlled via the bits shown in Figure 9. The extended mode regis-
ter is programmed via the LOAD MODE REGISTER command to the mode register (with
BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again
or the device loses power. The enabling of the DLL should always be followed by a LOAD
MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time before initiating any subse-
quent operation. Violating either of these requirements could result in unspecified oper-
ation.
The normal drive strength for all outputs are specified to be SSTL2, Class II. The x16 sup-
ports a programmable option for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The selection of the reduced
drive strength will alter the DQ pins and DQS pins from SSTL2, Class II drive strength to
a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive
strength.
When the part is running without the DLL enabled, device functionality may be altered.
The DLL must be enabled for normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur
before a READ command can be issued.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
Extended Mode Register
©2000 Micron Technology, Inc. All rights reserved.