MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 22

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

DESELECT
NO OPERATION (NOP)
LOAD MODE REGISTER
ACTIVE
READ
WRITE
PRECHARGE
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in
progress are not affected.
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
The mode registers are loaded via inputs A0–A11. See mode register descriptions in the
Register Definition section. The LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable command cannot be issued until
t
The ACTIVE command is used to open (or activate) a row in a particular bank for a sub-
sequent access. The value on the BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0–A11 selects the row. This row remains active (or open) for accesses
until a precharge command is issued to that bank. A precharge command must be
issued before opening a different row in the same bank.
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai (where i
= 8 for x16, 9 for x8, or 9, 11 for x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for subsequent accesses.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai
(where i = 8 for x16, 9 for x8, or 9, 11 for x4) selects the starting column location. The
value on input A10 determines whether or not auto precharge is used. If auto precharge
is selected, the row being accessed will be precharged at the end of the WRITE burst; if
auto precharge is not selected, the row will remain open for subsequent accesses. Input
data appearing on the DQ is written to the memory array subject to the DM input logic
level appearing coincident with the data. If a given DM signal is registered LOW, the cor-
responding data will be written to memory; if the DM signal is registered HIGH, the cor-
responding data inputs will be ignored, and a WRITE will not be executed to that byte/
column location.
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (
current auto precharge, where a READ or WRITE command to a different bank is allowed
as long as it does not interrupt the data transfer in the current bank and does not violate
MRD is met.
t
RP) after the precharge command is issued. Except in the case of con-
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands