MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 17

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Table 6:
Read Latency
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
Burst Length
2
4
8
Burst Definition
Notes: 1. Whenever a boundary of the block is reached within a given sequence above, the fol-
Starting Column Address
A2
0
0
0
0
1
1
1
1
2. For a burst length of two, A1-Ai select the two- data-element block; A0 selects the first
3. For a burst length of four, A2-Ai select the four- data-element block; A0-A1 select the
4. For a burst length of eight, A3-Ai select the eight- data-element block; A0-A2 select the
The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 2, 2.5, or
3 (DDR400 only) clocks, as shown in Figure 8.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 7, CAS Latency (CL),
on page 18 indicates the operating frequencies at which each CAS latency setting can be
used.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
lowing access wraps within the block.
access within the block.
first access within the block.
first access within the block.
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
17
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
Order of Accesses Within a Burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
Type = Interleaved
©2000 Micron Technology, Inc. All rights reserved.
Register Definition
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0