MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 27

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Figure 12:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
READ Command
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 17 on page 32. The BURST TERMINATE latency is equal to the read
(CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the
READ command, where x equals the number of desired data element pairs (pairs are
required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 18 on page 33. The
t
defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with, a PRECHARGE command to the
same bank provided that auto precharge was not activated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 19 on page 34. Following the PRECHARGE com-
mand, a subsequent command to the same bank cannot be issued until both
t
the last data elements.
x4: A0–A9, A11
DQSS (MAX) case has a longer bus idle time. (
RP has been met. Note that part of the row precharge time is hidden during the access of
x16: A9, A11
x16: A0–A8
x8: A0–A9
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
x8: A11
BA0,1
CAS#
RAS#
WE#
A10
CKE
CK#
CS#
CK
HIGH
DIS AP
DON’T CARE
EN AP
BA
CA
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
128Mb: x4, x8, x16 DDR SDRAM
DQSS [MIN] and
t
DQSS (NOM) case is shown; the
©2000 Micron Technology, Inc. All rights reserved.
t
DQSS [MAX] are
Operations
t
RAS and